TSMC has announced the completion and delivery of its 5nm design infrastructure within the Open Innovation Platform (OIP). This full release enables 5nm systems-on-chip (soC) designs for next generation mobile and high-performance computing (HPC) applications.The company's 5nm process is already in risk production and offers IC designers a new level of performance and power optimization.
Compared with TSMC’s 7nm process, its innovative scaling features deliver 1.8X logic density and 15% speed gain on an ARM Cortex-A72 core, along with superior SRAM and analog area reduction enabled by the process architecture. The 5nm process enjoys the benefits of process simplification provided by EUV lithography, and is making excellent progress in yield learning, achieving the best technology maturity at the same corresponding stage as compared to TSMC's previous nodes.
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